MARQUETTE, MICHIGAN, USA, July 18, 2022 /EINPresswire.com/ -- After 40+ years of R&D, Ronald Newman succeeded in manufacturing his first set of Super-Z Processors deploying his “lights-out” Si and SiC manufacturing processes.

Mr. Newman began Processor R&D coupled with OS, Compiler and EDA R&D in the early 80’s. Mr. Newman’s designs were initially realized with discrete & bit-slice components, then onto FPGA and Shared wafer macro blocks put down onto a PCB. After 40 years of iterative development, Mr. Newman’s Super-Z and Super-V series processors use from six-stage to thirty-two-stage superscalar pipelines and from two-super-threads to thirty-two-super-threads (extensions to both are in R&D) to provide unprecedent performance than any known processor to date by several orders of magnitude. As is commonly known, the current designs execute instructions issued in order and are allowed to complete out of order, a standard approach to dual-issue superscalar COTS designs as it provides reasonable performance with low silicon cost. Out-of-order completion prevents long-latency operations such as writes to memory from stalling the pipeline if there are no data dependencies. The Super-Z processors extended this concept by adding ‘context’ coupled with SIMD/MIMD to the various pipelines, units and the Super-V goes even further by redesigning with Super-VLIW instructions.

As most execution units are duplicated, the Super-Z was designed to be able to issue a plethora of combinations of instructions, so that it is not restricted to issuing the standard integer and floating-point instructions in parallel, etc. According to Mr. Newman and Colleagues, the current “lights-out” implementation of his base Super-Z can base clock at 400MHz (GHz+ speeds also realized) and obtained Coremarks greater than 2000 and up-to 5300, depending on the Super-Z blocks deployed. Further extensions and optimization are in progress to push for greater results.

The Super-Z on-chip flash coupled with a wealth of on-chip peripherals such-as quad-interrupt-controller (INTC), six versatile timers (TMU), quad-real-time clocks (RTC), quad serial interface channels (e.g., SCI, CAN), dual user break controller (UBC), and programmable power management controller are but a few of the many macro-blocks implemented on the die. The direct memory access controller (DMAC) has six channels. The DMAC is excellent for moving blocks of memory around with almost no CPU intervention needed. This makes for efficient transfers of data from main memory to graphics memory for example. Then there are the I/O units (IOU), Memory management units (MMU) and page-units (PU) which at the basic level were designed with memory protection and security in-mind, so different execution threads do not interfere with each other’s memory spaces and potentially induce operating system and application crashes.

The Super-Z base core includes DSP and GPU macro-blocks and excels at 3D calculations. The impressive 3D fixed/floating point hardware, where each of the four multipliers (f4muls) can receive two 32-bit (80-bit and fixed also supported) values and produce a multiplied result that is passed to a four-input- adders. This hardware reads two 128-bit vectors (two sets of four 32-bit values) out of register files, multiplies the four 32-bit pairs at the same time, adds the four products together, and puts the 32-bit result back into the register file. This provides the equivalent of 288-bit data crunching (2 x 128 + 32 = 288). This is just one pipeline of 3D calculations. The same functionality is applied to the DSP engines. And finally, the optional FPGA, PE-Array and MEMs macro-blocks can be utilized in generic logic/mixed, parallel-processing and/or mechanical/electrical implementations. Mr. Newman stated, “the beauty of designing using macro-blocks over 40+ years and limited resources, enabled my designs to be truly versatile and malleable, which enabled me to focus on R&D, not implementation. I continually and iteratively apply this methodology to all my R&D and Mathematics.”

With the current push to autonomy and safety, the Super-Z incorporates several safety-related features, including support for memory ECC and the ability to run eight-cores in lock-step with full data trace for debugging. And, Mr. Newman with colleagues are working to complete documentation of various mission-critical & mission-security standards such as ISO 26262/IEC62443 and extend LLVM (open-source compiler) to support the Super-Z base architecture.

Mr. Newman stated “finally I can replace all my FPGA/Macro/PCB HW with these Super-Z and Super-V processors to further enhance and extend the ‘lights-out’ concept and now extensively focus on R&D beginning with three of my many holy-grails: Energy, Recombinant DNA and Synthetic-Intelligence.”

Staff Writer
ZpNetics
zpiPRStaff@zpnetics.com